Technical Field
Various embodiments of the disclosure and their implementation relate to non-volatile memory devices, notably those comprising buried selection transistors and, more particularly, the improvement of the read performance of such devices by reducing, or even eliminating, the stress induced in the floating gate of the state transistor of a memory cell during an operation for reading this memory cell.
Description of the Related Art
A non-volatile memory cell, whether it is of the electrically erasable and programmable (EEPROM) type or else of the type with vertical selection transistor, comprises a state transistor with a floating gate selectable by means of a selection transistor connected in series with the state transistor.
The logical value of a bit stored in such a memory cell is represented by the value of the threshold voltage of the floating gate transistor.
The programming or the erasing of a floating gate transistor consists of the injection or the extraction of the electrical charges into/from the gate of the transistor by tunnel effect (Fowler-Nordheim effect) or by injection of hot electrons by means of high voltage(s).
Furthermore, the reading of such a memory cell may be carried out by applying a read voltage to the control gate of the floating gate state transistor, together with a positive voltage to the bit line connected to the drain of this floating gate transistor.
However, when such a read voltage is applied to the control gate of the state transistor, the electric field in the floating gate is modified resulting in a stress, which ‘read stress’ may lead to a ‘read disturb’ phenomenon that can result in a modification of the logical value of the stored bit.